Bootcamps
Coming soon · the subjects below are what they will draw on
Subjects
What it is
Circuit laws, components and their terminal behaviour, analog signal circuits and operational amplifiers, transient and steady-state analysis, on paper and on the bench.
Where it sits
School of Hardware & Electronics · Core
Crunch Circuits — Electronics & PCB Design
You get
Reasoning about circuits from Ohm's and Kirchhoff's laws, choosing components from their datasheets and ratings, first-order transients, filters and op-amp stages, regulated power and decoupling, and every prediction checked against a simulator and then a bench measurement.
What it is
Number representation, assembly, the datapath, pipelining, caches, and how code becomes hardware behaviour.
Where it sits
School of Hardware & Electronics · Core
Crunch Silicon — Digital Logic, FPGA & Verilog
You get
A computer built from the transistor up — gates, combinational and sequential logic, finite state machines, arithmetic hardware and memory — ending in a pipelined CPU you designed and verified in Verilog.
Still to add
Assembly-language programming against a commercial ISA, and cache-performance measurement on real hardware.
What it is
Boolean algebra, combinational and sequential circuits, state machines, and HDL basics.
Where it sits
School of Hardware & Electronics · Core
Crunch Silicon — Digital Logic, FPGA & Verilog
You get
Thinking in gates, combinational and sequential logic, real Verilog, verification the way an engineer does it, finite state machines, arithmetic hardware and memory.
What it is
The first-year drafting-and-modelling course every engineering programme requires: constrained sketching, parametric solid modelling, assemblies, and a dimensioned drawing a shop can build from. C12 covers the modelling half deeper than the course does and leaves the pencil-and-paper half short; it is taught on Onshape, which is free but proprietary, and whose free plan makes every document you create public.
Where it sits
School of Hardware & Electronics · Intro
You get
Six weeks of parametric solid modelling on Onshape - constrained sketching, extrudes and revolves, construction planes, patterns, sweeps and lofts, assemblies mated to an exact degree-of-freedom count, drawings with section views, GD&T and a bill of materials, variable-driven configured part families, and an original multi-part mechanism released at a tagged version with STEP and STL exports somebody else has opened.
Still to add
Freehand technical sketching as a drilled skill, spatial visualisation exercises such as supplying a missing view, auxiliary views of an inclined face, classical descriptive geometry, limits-and-fits tables and a tolerance stack-up calculation, and product verification - inspecting a made part against its drawing. Separately: no assigned problem outside the quizzes carries a published worked solution, and the setup guides are another course's.
What it is
Describing digital systems in Verilog and SystemVerilog, verifying them, closing timing, and running the whole flow onto a real FPGA.
Where it sits
School of Hardware & Electronics · Upper level
Not ready yet · on the build list
You get
Twelve weeks of register-transfer-level design on real fabric — combinational and sequential logic, state machines, self-checking and formal verification, timing constraints and closure, block RAM and FIFOs, pipelining, clock-domain crossing, UART, SPI and I2C, a soft core on a bus, and a capstone accelerator you synthesize and run.
Still to add
The ASIC back end and design for test; power and area as graded design constraints, where Week 06 grades frequency alone; UVM's class-based agent, driver, monitor and scoreboard architecture; external memory controllers such as SDRAM and DDR, where Week 07 stops at on-chip block RAM; translating a C or C++ application into a hardware model. On the industry side, a continuous-integration unit and a shipped linter or formatter configuration. Largest of all: no problem page yet publishes its worked answer under a visible Solution heading.
DM us to ask for it — requests decide the order
What it is
Capturing a schematic in a CAD package, laying out and routing a board, producing the outputs a fabricator needs, and assembling and testing what comes back.
Where it sits
School of Hardware & Electronics · Core
Crunch Circuits — Electronics & PCB Design
You get
A schematic captured in KiCad with real symbols, nets and footprints and an electrical-rules check behind it, a board placed, routed and plane-poured to a passing design-rule check, Gerbers, drill files, a bill of materials and pick-and-place data a fab will accept, and the returned board hand-soldered, inspected, powered up and debugged.
What it is
Transistor-level design, fabrication constraints, timing, power, and the physical layer of a chip.
Where it sits
School of Hardware & Electronics · Upper level
Crunch Silicon — Digital Logic, FPGA & Verilog
You get
The digital-design half: gates, Verilog, verification, state machines, arithmetic units, memory and a pipelined CPU.
Still to add
Transistor-level design, standard-cell layout, timing closure, power analysis and the fabrication process.